VeeR EH1 core
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Updated
May 29, 2023 - SystemVerilog
VeeR EH1 core
VeeR EL2 Core
Quasar 2.0: Chisel equivalent of SweRV-EL2
Attempt to develop a verification IP and plan for a bus functional model of ARM based AMBA 3 AHB-LITE Protocol. Implemented object oriented programming techniques in SysteVerilog.
Verilog AHB Bus implementation for VAAMAN
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