AArch64: Change rmif bit shift to rotate #6589
Open
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
ryanmkurtz
added
Feature: Processor/AARCH64
Status: Triage
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the rmif instruction for AARCH64. According to Section C6.2.260, the expected behaviour is to rotate right the value in the operand register, and the lower bits are copied into the NZCV flags. While the current behaviour instead performs a right shift, clearing some bits when the shift immediate is greater than 60.
e.g.:
0xcf871fba"rmif x30, #0x3f, #0xf" with x30 = 0x5f6d9d6c85ec78e5Hardware Reference: NZCV = 0xa
Existing Spec: NZCV = 0x0
Patched Spec: NZCV = 0xa