i#3544 RV64 vector part2: Add basic vector support to the core

[ksco]

This is a follow-up patch of adding RISC-V vector (RVV) extension support to the core, part1 in PR #6810 (f1ce1bc).

This patch:

1. fixes several issues in the codec introduced in part1, codec unit tests will be submitted separately in follow-up PRs;
2. rename and reuse SVE vector length getter/setter functions to be more concise on APIs for vector extensions;
3. adds RISC-V vector support to drdisas;
4. support code cache and clean call context switch;

For now, we support RISC-V vector lengths up to 256 bits, longer vector lengths will exceed the limit of DynamoRIO stack size and 12-bit signed immediate range.

Issue: #3544

[derekbruening]

(May not get to this for another day)

[derekbruening]

Main concern is the 8-vector-reg stride on all the loops: is that right?

[derekbruening]

May want to have the Arm folks have a look mostly as a heads up on the vector length API name changes: I'll add @AssadHashmi

[derekbruening]

Unless I'm missing something, the reg_get_size_lmul looks incorrect.

[AssadHashmi]

May want to have the Arm folks have a look mostly as a heads up on the vector length API name changes: I'll add @AssadHashmi

I have been on vacation. The name changes are fine with us.