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179 public repositories
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Functional verification project for the CORE-V family of RISC-V cores.
Updated
Jun 28, 2024
Assembly
Updated
Jun 28, 2024
SystemVerilog
Updated
Jun 28, 2024
SystemVerilog
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Updated
Jun 27, 2024
Python
Standard Universal Verification Methodology
Updated
Jun 27, 2024
SystemVerilog
Multi-Processor System on Chip verified with UVM/OSVVM/FV
Updated
Jun 27, 2024
SystemVerilog
System on Chip verified with UVM/OSVVM/FV
Updated
Jun 27, 2024
SystemVerilog
Processing Unit verified with UVM/OSVVM/FV
Updated
Jun 27, 2024
SystemVerilog
Design & Verification of IP Cores and ICs, Artificial Intelligence
Updated
Jun 23, 2024
VHDL
Updated
Jun 19, 2024
SCSS
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Updated
Jun 18, 2024
SystemVerilog
A gateway for amazing Web1337 by KLYNTAR
Updated
Jun 14, 2024
JavaScript
Code generation tool for control and status registers
Updated
Jun 11, 2024
Ruby
Universal Virtual Machine for Node and Browser
Updated
Jun 21, 2024
JavaScript
SystemVerilog RTL and UVM RAL model generators for RgGen
Updated
Jun 7, 2024
SystemVerilog
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Updated
Jun 6, 2024
Python
🎨 Colorize your boring EDA logs
Updated
May 26, 2024
Shell
in this repository is there in how to write virtual interface
Updated
May 18, 2024
SystemVerilog
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