DDR2 memory controller written in Verilog
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Updated
Feb 28, 2012 - Verilog
DDR2 memory controller written in Verilog
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
mirror of https://git.elphel.com/Elphel/eddr3
Java applet code and Arduino code for musical mat project
A Game Programming final created in Processing. DDR but on keyboard without music syncronization
DDAL(Distributed Data Access Layer) is a simple solution to access database shard.
A small collection of old 8 on the Break tournament results.
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
What happends when you mix up DDR + A simple calulcator? Done in VUE.js
Pattern generator for StepMania charts with existing rhythm/notes
Working fork of TapMania for iOS 9.3 and above.
Beat extractor for DDR game
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
Hardware and Software Co-design implementations
OpenDDR C# Clients
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