{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":184654298,"defaultBranch":"main","name":"wasm-micro-runtime","ownerLogin":"bytecodealliance","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2019-05-02T21:32:09.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/54038801?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1719284663.0","currentOid":""},"activityList":{"items":[{"before":null,"after":"867dbd8912f8fd489ea9b24497abb9d3c81f1b40","ref":"refs/heads/dev/multi_memory","pushedAt":"2024-06-25T03:04:23.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"wenyongh","name":"Wenyong Huang","path":"/wenyongh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20393758?s=80&v=4"},"commit":{"message":"aot compiler: Propagate const-ness by ourselves (#3567)\n\naot_load_const_from_table() hides the const-ness of the\r\nvalue and prevents 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1)\r\n)\r\n```\r\n\r\nWhile the address (0x104) is perfectly aligned for i32.store,\r\nas our aot compiler uses 1-byte alignment for load/store LLVM\r\nIR instructions, it often produces inefficient machine code,\r\nespecially for alignment-sensitive targets.\r\n\r\nFor example, the above \"foo\" function is compiled into the\r\nfollowing xtensa machine code.\r\n```\r\n0000002c <aot_func_internal#0>:\r\n  2c:   004136          entry   a1, 32\r\n  2f:   07a182          movi    a8, 0x107\r\n  32:   828a            add.n   a8, a2, a8\r\n  34:   291c            movi.n  a9, 18\r\n  36:   004892          s8i     a9, a8, 0\r\n  39:   06a182          movi    a8, 0x106\r\n  3c:   828a            add.n   a8, a2, a8\r\n  3e:   ffff91          l32r    a9, 3c <aot_func_internal#0+0x10> (ff91828a <aot_func_internal#0+0xff91825e>)\r\n                        3e: R_XTENSA_SLOT0_OP   .literal+0x8\r\n  41:   004892          s8i     a9, a8, 0\r\n  44:   05a182          movi    a8, 0x105\r\n  47:   828a            add.n   a8, a2, a8\r\n  49:   ffff91          l32r    a9, 48 <aot_func_internal#0+0x1c> (ffff9182 <aot_func_internal#0+0xffff9156>)\r\n                        49: R_XTENSA_SLOT0_OP   .literal+0xc\r\n  4c:   41a890          srli    a10, a9, 8\r\n  4f:   0048a2          s8i     a10, a8, 0\r\n  52:   04a182          movi    a8, 0x104\r\n  55:   828a            add.n   a8, a2, a8\r\n  57:   004892          s8i     a9, a8, 0\r\n  5a:   f01d            retw.n\r\n```\r\n\r\nNote that the each four bytes are stored separately using\r\none-byte-store instruction, s8i.\r\n\r\nThis commit tries to use larger alignments for load/store LLVM IR\r\ninstructions when possible.  with this commit, the above example is\r\ncompiled into the following machine code, which seems more reasonable.\r\n```\r\n0000002c <aot_func_internal#0>:\r\n  2c:   004136          entry   a1, 32\r\n  2f:   ffff81          l32r    a8, 2c <aot_func_internal#0> (81004136 <aot_func_internal#0+0x8100410a>)\r\n              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